Explaining RISC-V: An x86 & ARM Alternative

From the creator

RISC-V is an alternative microprocessor technology to x86 and ARM, with its instruction set architecture (ISA) being open rather than closed. This video explains what RISC-V is all about, including its origins, key market players, hardware, applications, intellectual property (IP), and the likely role of global politics and international trade barriers in determining RISC-V’s success. Note that I have posted a "RISC-V 2024 Update" video here: https://www.youtube.com/watch?v=f6mPK3QCrBo -- and a "RISC-V 2023 Update" video here: https://www.youtube.com/watch?v=AJVSZEX6d9M My previous review of the VisionFive RISC-V SBC that can run a Linux OS is here: https://www.youtube.com/watch?v=4PoWAsBOsFs And my review of the Nezha RISC-V SBC that can also run a Linux OS is here: https://www.youtube.com/watch?v=613yEF6SrNo REFERENCES Specific sources included in the video are as follows: RISC-V International: https://riscv.org/ The first RISC-V Instruction Set Manual (from 2011): https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-62.pdf SiFive website: https://www.sifive.com/ and RISC-V core IP: https://www.sifive.com/risc-v-core-ip SiFive development boards: https://www.sifive.com/boards Samsung to use SiFive RISC-V cores: https://riscv.org/news/2019/12/samsung-to-use-sifive-risc-v-cores-for-socs-automotive-5g-applications-anton-shilov-anandtech/ T-Head Xuantie product overview: https://www.t-head.cn/product/overview Alibaba (T-Head) open sources Xuantie RISC-V cores:

Published 2022-05-08 · Watch on YouTube ↗
Availability and playback restrictions are controlled by the original channel.